1. Field of the Invention
The present invention relates to a display device which displays an image by pixels disposed so as to be in a matrix. For example, the invention disclosed herein is applicable to an active matrix liquid crystal display device and an EL (electro-luminescent) display.
2. Description of the Related Art
Conventionally, active matrix liquid crystal display devices have been known. Such a display device is structured such that thin film transistors for switching are disposed for respective pixel electrodes disposed in a matrix of several hundreds x several hundreds or more, and that electric charge retained at the respective pixel electrodes is controlled by the thin film transistors.
In order to display a picture of high quality, how finely gradation display can be carried out is important.
FIG. 3 illustrates a structure of a classical active matrix liquid crystal display device. A shift register and a buffer circuit generally referred to as a peripheral driving circuit are formed by disposing exterior type IC circuits on a substrate.
Further, thin film transistors 1 utilizing amorphous semiconductor formed on a glass substrate are disposed with regard to the respective pixels in the active matrix circuit. A liquid crystal cell 2 comprising a pixel electrode, liquid crystal, and a counter electrode is connected with each of the thin film transistors 1.
Another structure is also known in which quartz is utilized as a substrate and a thin film transistor is formed with a crystalline semiconductor film. In this case, both the peripheral driving circuit and the active matrix circuit comprising thin film transistors formed on a quartz substrate.
Still a technique is also known that a thin film transistor is formed with a crystalline semiconductor film on a glass substrate by utilizing such as laser annealing. Such a technique makes it possible to integrate the active matrix circuits and the peripheral driving circuit on a glass substrate.
In a structure as shown in FIG. 3, by a signal from a shift register circuit 11 of a source driver (a shift register for horizontal scanning), a picture signal 13 to be supplied to a picture signal line 12 is selected according to timing shown in FIG. 3B. Then, a predetermined picture signal is supplied to a corresponding source signal line 14.
The picture signal 13 supplied to the source signal line 14 is selected by the thin film transistor 1 to be written in a predetermined pixel electrode.
The thin film transistor is operated according to a selection signal supplied via a gate signal line 15 from a shift register of a gate driver (a shift register for vertical scanning) which is not shown.
By sequentially and repeatedly carrying out the above-mentioned operation according to appropriately set timing based on signals from the shift register 11 of the source driver and from the shift register of the gate driver, information is sequentially written to the respective pixels disposed so as to be in a matrix.
After pixel information for one picture is written, pixel information for the subsequent picture is written. In this way, pictures are displayed one after another. Typically, writing of information for one picture is carried out 30 times or 60 times per second.
In such operation, in order to carry out gradation display, a picture signal is required to include a signal corresponding to the necessary gradation.
In case a signal supplied to the device is an analog signal, since the signal includes a signal necessary for gradation display, even the structure shown in FIG. 3A can accommodate gradation display to some extent.
However, in case display is carried out based on a digital signal from a magnetic recording medium, a digital circuit or the like, a problem arises with the structure shown in FIG. 3A.
In case the base signal is digital, an analog picture signal as shown in FIG. 3B must be produced by a D/A converter.
The number of levels of gradation necessary for a portable information processing terminal or the like is 64 or more. However, if a picture signal including information for 64 levels of gradation is to be produced by a D/A converter, there is a problem that the structure of the D/A converter is required to be complicated, which leads to higher cost.
Especially in case the display device is highly integrated, the D/A converter is also required to be formed on a panel with a thin film transistor. However, it is very difficult to form the D/A converter for producing information for 64 levels of gradation as described above by using a thin film transistor.
For example, suppose the XGA standard (1024.times.768 pixels) is adopted to write a picture 60 times per second. In this case, it takes ((1/60)/768) sec, i.e., 21.7 .mu.sec to sequentially supply a signal from the first to the 1024th source signal lines in one line.
Further, time period from a time when a shift register of the n th stage starts its operation to a time when a shift register of the (n+1) th stage starts its operation is 1/1024 thereof, i.e., 21.2 .mu.nsec, which means that the operation speed of 47 MHz or more is required.
Even just to produce an analog signal corresponding to 64 levels of gradation at an operating speed of about 47 MHz is burdensome for a D/A converter. Thus, it goes without saying that it is very difficult to form a D/A converter having such ability with a thin film transistor.